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1 el5220t 12mhz rail-to-rail input-output operational amplifier el5220t the el5220t is a high voltage rail-to-rail input-output amplifier with low power consumption. the el5220t contains two amplifiers. each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. the maximum operating voltage range is from 4.5v to 19v. it can be configured for single or dual supply operation, and typically consumes only 550 a per amplifier. the el5220t has an output short circuit capability of 200ma and a continuous output current capability of 65ma. the el5220t features a slew rate of 12v/ s. also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12mhz (-3db). this enables the amplifiers to offer maximum dynamic range at any supply voltage. these features make the el5220t an ideal amplifier solution for use in tft-lcd panels as a v com or static gamma buffer, and in high speed filtering and signal conditioning applications. other applications include battery power and portable devices, especially where low power consumption is important. the el5220t is available in an 8 ld msop package, and a thermally enhanced 8 ld dfn package. both feature a standard operational amplifier pinout. the devices operate over an ambient temperature range of -40c to +85c. features ? 12mhz (-3db) bandwidth ? 4.5v to 19v maximum supply voltage range ? 12v/ s slew rate ? 550 a supply current (per amplifier) ? 65ma continuous output current ? 200ma output short circuit current ? unity-gain stable ? beyond the rails input capability ? rail-to-rail output swing ? built-in thermal protection ? -40c to +85c ambient temperature range ? pb-free (rohs compliant) applications* (see page 13) ? tft-lcd panels ?v com amplifiers ? static gamma buffers ? electronics notebooks ? electronics games ? touch-screen displays ? personal communication devices ? personal digital assistants (pda) ? portable instrumentation ? sampling adc amplifiers ? wireless lans ? office automation ? active filters ? adc/dac buffer figure 1. typical tft-lcd v com application figure 2. frequency response for various r l +15v 4.7 f 0.1 f panel tft-lcd panel capacitance vouta vina- vina+ vs- vs+ voutb vinb- vinb+ + panel capacitance 0 0 el5220t +15v -15 -10 -5 0 5 100k 1m 10m 100m frequency (hz) normalized gain (db) 1k 560 150 v s = 5v a v = 1 c l = 8pf 10k caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. may 4, 2010 fn6892.0
el5220t 2 fn6892.0 may 4, 2010 pin configuration el5220t (8 ld msop) top view el5220t (8 ld dfn) top view vs+ voutb vinb- vinb+ vs- vina+ vina- vouta 1 2 3 4 8 7 6 5 - + - + 2 3 4 1 7 6 5 8 vouta vina- vina+ vs- vs+ voutb vinb- vinb+ pd thermal pad is electrically connected to vs- pin descriptions pin number (msop, dfn) pin name function equivalent circuit 1 vouta amplifier a output (reference circuit 1) 2 vina- amplifier a inverting input (reference circuit 2) 3 vina+ amplifier a non-inverting input (reference circuit 2) 4 vs- negative power supply 5 vinb+ amplifier b non-inverting input (reference circuit 2) 6 vinb- amplifier b inverting input (reference circuit 2) 7 voutb amplifier b output (reference circuit 1) 8 vs+ positive power supply pd thermal pad functions as a heat sink. electrically connected to vs-. connect the thermal pad to vs- plane on the pcb for optimum thermal performance. v s+ gnd v s- circuit 1 v s+ v s- circuit 2 v outx v inx ordering information part number (notes 2, 3) part marking package (pb-free) pkg. dwg. # el5220tilz-t13 (note 1) 20t 8 ld dfn l8.2x3 el5220tiyz bbbma 8 ld msop m8.118a EL5220TIYZ-T7 (note 1) bbbma 8 ld msop m8.118a el5220tiyz-t13 (note 1) bbbma 8 ld msop m8.118a notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for el5220t . for more information on msl please see techbrief tb363 .
el5220t 3 fn6892.0 may 4, 2010 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unle ss otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = +25c) thermal information supply voltage between v s + and v s - . . . . . . . . . . . .+19.8v input voltage range (v inx+ , v inx- ) . . . v s - - 0.5v, v s + + 0.5v input differential voltage (v inx+ - v inx- ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v s + + 0.5v)-(v s - - 0.5v) maximum continuous output current . . . . . . . . . . .65ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . 3000v thermal resistance (typical) ja (c/w) jc (c/w) 8 ld msop (notes 6, 7) . . . . . . . . 170 60 8 ld dfn (notes 4, 5) . . . . . . . . . . 58 8 storage temperature . . . . . . . . . . . . . . . -65c to +150c ambient operating temperature . . . . . . . . . -40c to +85c maximum junction temperature . . . . . . . . . . . . . . . +150c power dissipation . . . . . . . . . . . . . . . see figures 32 and 33 pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www .intersil.com/pbfree/pb-freer eflow .asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is taken at the package top center. electrical specifications v s + = +5v, v s - = -5v, r l = 10k to 0v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 0v 3 18 mv tcv os average offset voltage drift (note 8) 8 ld msop package 5 v/c 8 ld dfn package 3 v/c i b input bias current v cm = 0v 2 50 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -5.5 +5.5 v cmrr common-mode rejection ratio for v inx from -5.5v to +5.5v 50 75 db a vol open loop gain -4.5v v outx + 4.5v 75 105 db output characteristics v ol output swing low i l = -5ma -4.94 -4.85 v v oh output swing high i l = +5ma 4.85 4.94 v i sc short circuit current v cm = 0v, source: v outx short to v s -, sink: v outx short to v s + 200 ma i out output current 65 ma power supply performance (v s +) - (v s -) supply voltage range 4.5 19 v i s supply current (per amplifier) v cm = 0v, no load 550 750 a psrr power supply rejection ratio supply is moved from 2.25v to 9.5v 60 75 db
el5220t 4 fn6892.0 may 4, 2010 dynamic performance sr slew rate (note 9) -4.0v v outx + 4.0v, 20% to 80% 12 v/ s t s settling to +0.1% (note 10) a v = +1, v outx = 2v step, r l = 10k , c l = 8pf 500 ns bw -3db bandwidth r l = 10k , c l = 8pf 12 mhz gbwp gain-bandwidth product a v = -50, r f = 5k , r g = 100 r l = 10k , c l = 8pf 8 mhz pm phase margin a v = -50, r f = 5k , r g = 100 r l = 10k , c l = 8pf 50 cs channel separation f = 5mhz 85 db electrical specifications v s + = +5v, v s - = -5v, r l = 10k to 0v, t a = +25c, unless otherwise specified. (continued) parameter description conditions min typ max unit electrical specifications v s + = +5v, v s - = 0v, r l = 10k to 2.5v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 2.5v 3 18 mv tcv os average offset voltage drift (note 8) 8 ld msop package 5 v/c 8 ld dfn package 3 v/c i b input bias current v cm = 2.5v 2 50 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -0.5 +5.5 v cmrr common-mode rejection ratio for v inx from -0.5v to +5.5v 45 70 db a vol open loop gain 0.5v v outx + 4.5v 75 105 db output characteristics v ol output swing low i l = -2.5ma 30 150 mv v oh output swing high i l = +2.5ma 4.85 4.97 v i sc short circuit current v cm = 2.5v, source: v outx short to v s -, sink: v outx short to v s + 125 ma i out output current 65 ma power supply performance (v s +) - (v s -) supply voltage range 4.5 19 v i s supply current (per amplifier) v cm = 2.5v, no load 550 750 a psrr power supply rejection ratio supply is moved from 4.5v to 19v 60 75 db dynamic performance sr slew rate (note 9) 1v v outx 4v, 20% to 80% 12 v/ s t s settling to +0.1% (note 10) a v = +1, v outx = 2v step, r l = 10k , c l = 8pf 500 ns bw -3db bandwidth r l = 10k , c l = 8pf 12 mhz gbwp gain-bandwidth product a v = -50, r f = 5k , r g = 100 r l = 10k , c l = 8pf 8 mhz pm phase margin a v = -50, r f = 5k , r g = 100 r l = 10k , c l = 8pf 50 cs channel separation f = 5mhz 85 db
el5220t 5 fn6892.0 may 4, 2010 electrical specifications v s + = +18v, v s - = 0v, r l = 10k to 9v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 9v 5 18 mv tcv os average offset voltage drift (note 8) 8 ld msop package 6 v/c 8 ld dfn package 4 v/c i b input bias current v cm = 9v 2 50 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -0.5 +18.5 v cmrr common-mode rejection ratio for v inx from -0.5v to +18.5v 53 78 db a vol open loop gain 0.5v v outx 17.5v 75 90 db output characteristics v ol output swing low i l = -9ma 120 150 mv v oh output swing high i l = +9ma 17.85 17.88 v i sc short circuit current v cm = 9v, source: v outx short to v s -, sink: v outx short to v s + 200 ma i out output current 65 ma power supply performance (v s +) - (v s -) supply voltage range 4.5 19 v i s supply current (per amplifier) v cm = 9v, no load 650 850 a psrr power supply rejection ratio supply is moved from 4.5v to 19v 60 75 db dynamic performance sr slew rate (note 9) 1v v outx 17v, 20% to 80% 12 v/ s t s settling to +0.1% (note 10) a v = +1, v outx = 2v step, r l = 10k , c l = 8pf 500 ns bw -3db bandwidth r l = 10k , c l = 8pf 12 mhz gbwp gain-bandwidth product a v = -50, r f = 5k , r g = 100 r l = 10k , c l = 8pf 8 mhz pm phase margin a v = -50, r f = 5k , r g = 100 r l = 10k , c l = 8pf 50 cs channel separation f = 5mhz 85 db notes: 8. measured over -40c to +85c ambient operating temperature range. see the typical tcv os production distribution shown in the ?typical performance curves? on page 6. 9. typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal. 10. settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the ou tput level settles within a 0.1% error band. the range of the error band is determined by: final value(v) [full scale(v) * 0.1%]
el5220t 6 fn6892.0 may 4, 2010 typical performance curves figure 3. input offset voltage distribution figure 4. input offset voltage drift (msop) figure 5. input offset voltage drift (dfn) figure 6. input offset voltage vs temperature figure 7. input bias current vs temperature figure 8. output high voltage vs temperature 0 100 200 300 400 500 -10 -8 -6 -4 -2 0 4 6 10 input offset voltage (mv) quantity (amplifiers) v s = 5v t a = +25c typical production distribution 28 0 2 4 6 8 10 12 14 16 18 2 4 6 8 101214161820222426 28 input offset voltage drift (| v |/c) typical production distribution v s = 5v -40c to +85c quantity (amplifiers) 0 2 4 6 8 10 12 14 16 18 15911131517 input offset voltage drift (mv) quantity ( amplifiers) typical production distribution v s = 5v -40c to +85c 37 0.0 2.5 5.0 7.5 10.0 -50 0 50 100 150 temperature (c) input offset voltage (mv) v s = 5v -1 0 1 2 3 4 5 -50 0 50 100 150 input bias current (na) v s = 5v temperature (c) 4.92 4.93 4.94 4.95 4.96 -50 0 50 100 150 output high voltage (v) temperature (c) v s = 5v i out = 5ma
el5220t 7 fn6892.0 may 4, 2010 figure 9. output low voltage vs temperature figure 10. open-loop gain vs temperature figure 11. slew rate vs temperature figure 12. supply current per amplifier vs temperature figure 13. supply current per amplifier vs supply voltage figure 14. slew rate vs supply voltage typical performance curves (continued) -4.91 -50 0 50 100 150 temperature (c) v s = 5v i out = -5ma -4.92 -4.93 -4.94 -4.95 -4.96 -4.97 output low voltage (v) 40 60 80 100 120 140 -50 0 50 100 150 open loop gain (db) temperature (c) v s = 5v r l = 10k 11.0 11.5 12.0 12.5 13.0 -50 0 50 100 150 slew rate (v/ s) temperature (c) v s = 5v r l = 10k 510 530 550 570 590 supply current ( a) v s = 5v no load input at gnd -50 0 50 100 150 temperature (c) 400 500 600 700 800 24 10 supply voltage (v) t a = +25c no load input at gnd supply current ( a) 68 8 10 12 14 16 4 6 8 101214161820 t a = +25c a v = 1 r l = 10k c l = 8pf slew rate (v/ s) supply voltage (v)
el5220t 8 fn6892.0 may 4, 2010 figure 15. open loop gain and phase vs frequency figure 16. frequency response for various r l figure 17. frequency response for various c l figure 18. closed loop output impedance vs frequency figure 19. maximum output swing vs frequency figure 20. cmrr vs frequency typical performance curves (continued) -20 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open loop gain (db) -50 0 50 100 150 200 250 phase () v s = 5v t a = +25c r l = 10k c l = 8pf phase gain -15 -10 -5 0 5 100k 1m 10m 100m normalized gain (db) frequency (hz) 1k 560 150 v s = 5v a v = 1 c l = 8pf 10k -15 -10 -5 0 5 10 15 20 100k 1m 10m 100m 8pf 50pf 100pf frequency (hz) normalized gain (db) v s = 5v a v = 1 r l = 10k 1000pf 0.01 0.1 10 100 1000 10 1k 100k 1m 100m frequency (hz) v s = 5v r f = 2kv r g = 1k r l = 450 source = 0dbm output impedance ( ) 1 0 2 4 6 8 10 12 10k 100k 1m 10m frequency (hz) maximum output swing (v p-p ) v s = 5v t a = +25c a v = 1 r l = 10k c l = 8pf -80 -70 -60 -50 -40 -30 -20 -10 0 10 1k 100k 100m cmrr (db) frequency (hz) v s = 5v t a = +25c v inx = -10dbm
el5220t 9 fn6892.0 may 4, 2010 figure 21. psrr vs frequency figure 22. input voltage noise spectral density vs frequency figure 23. total harmonic distortion + noise vs frequency figure 24. channel separation vs frequency response figure 25. small signal overshoot vs load capacitance figure 26. step size vs settling time typical performance curves (continued) -80 -70 -60 -50 -40 -30 -20 -10 0 1k 10k 100k 1m 10m psrr (db) v s = 5v t a = +25c frequency (hz) 1 10 100 1000 100 1k 10k 100k 1m 10m 100m frequency (hz) voltage noise (nv/ hz) t a = +25c 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 100 1k 10k 100k frequency (hz) thd+n (%) v s = 5v r l = 10k a v = 1 v in = 1.4v rms -100 -90 -80 -70 -60 10k 100k 1m 10m frequency (hz) xtalk (db) v s = 5v a v = 1 v inx = 0dbm 0 20 40 60 80 100 10 100 1000 load capacitance (pf) overshoot (%) v s = 5v t a = +25c a v = 1 r l = 10k v inx = 50mv -5 -4 -3 -2 -1 0 1 2 3 4 5 100 200 300 400 500 600 700 settling time (ns) step size (v) v s = 5v t a = +25c a v = 1 r l = 10k c l = 8pf 0.1% 0.1%
el5220t 10 fn6892.0 may 4, 2010 figure 27. large signal transient response figure 28. small signal transient response figure 29. basic test circuit typical performance curves (continued) 6v step 1 s/div 1v/div v s = 5v t a = +25c a v = 1 r l = 10k c l = 8pf v s = 5v t a = +25c a v = 1 r l = 10k c l = 8pf 100mv step 50mv/div 200ns/div vina+ vouta thermal pad connected to v s - (dfn only) 49.9 voutb el5220t (8ld msop/dfn shown) vinb+ 49.9 4.7 f 0.1 f + r fa vouta vina- vina+ voutb vinb- vinb+ 1 2 3 7 6 5 4 4.7 f 0.1 f + 8 r la r ga c la v s - v s - v s + r gb r lb r fb c lb v s +
el5220t 11 fn6892.0 may 4, 2010 applications information product description the el5220t is a high voltage rail-to-rail input-output amplifier with low power consumption. the el5220t contains two amplifiers. each amplifier exhibits beyond the rail input capability, rail-to-rail output capability, and is unity gain stable. the el5220t features a slew rate of 12v/ s. also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12mhz (-3db). this enables the amplifiers to offer maximum dynamic range at any supply voltage. operating voltage, input and output capability the el5220t can operate on a single supply or dual supply configuration. the el5220t operating voltage ranges from a minimum of 4.5v to a maximum of 19v. this range allows for a standard 5v (or 2.5v) supply voltage to dip to -10%, or a standard 18v (or 9v) to rise by +5.5% without affecting performance or reliability. the input common-mode voltage range of the el5220t extends 500mv beyond the supply rails. also, the el5220t is immune to phase reversal. however, if the common mode input voltage exceeds the supply voltage by more than 0.5v, electrostatic protection diodes in the input stage of the device begin to conduct. even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. figure 30 shows the input voltage driven 500mv beyond the supply rails and the device output swinging between the supply rails. the el5220t output typically swings to within 50mv of positive and negative supply rails with load currents of 5ma. decreasing load currents will extend the output voltage range even closer to the supply rails. figure 31 shows the input and output waveforms for the device in a unity-gain configuration. operation is from 5v supply with a 10k load connected to gnd. the input is a 10v p-p sinusoid and the output voltage is approximately 9.9v p-p . refer to the ?electrical specifications? table beginning on page 3 for specific device parameters. parameter variations with operating voltage, loading and/or temperature are shown in the ?typical performance curves? on page 6. output current the el5220t is capable of output short circuit currents of 200ma (source and sink), and the device has built-in protection circuitry which limits the output current to 200ma (typical). to maintain maximum reliability the continuous output current should never exceed 65ma. this 65ma limit is determined by the characteristics of the internal metal interconnects. also, see ?power dissipation? on page 12 for detailed information on ensuring proper device operation and reliability for temperature and load conditions. unused amplifiers it is recommended that any unused amplifiers be configured as a unity gain follower. the inverting input should be directly connected to the output and the non-inverting input tied to the ground. thermal shutdown the el5220t has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. when the die temperature reaches +165c (typical) the device automatically shuts off the outputs by putting them in a high impedance state. when the die cools by +15c figure 30. operation with beyond-the-rails input 1v/div v s = 2.5v, t a = +25c, a v = 1, v inx = 6v p-p, r l = 10k to gnd input output 100 s/div figure 31. operation with rail-to-rail input and output v s = 5v, t a = +25c, a v = 1, v inx = 10v p-p, r l = 10k to gnd 5v/div input output 100 s/div
el5220t 12 fn6892.0 may 4, 2010 (typical) the device automatically turns on the outputs by putting them in a low impedance (normal) operating state. driving capacitive loads as load capacitance increases, the -3db bandwidth will decrease and peaking can occur. depending on the application, it may be necessary to reduce peaking and to improve device stability. to improve device stability, a snubber circuit or a series resistor may be added to the output of the el5220t. a snubber is a shunt load consisting of a resistor in series with a capacitor. an optimized snubber can improve the phase margin and the stability of the el5220t. the advantage of a snubber circuit is that it does not draw any dc load current or reduce the gain. another method to reduce peaking is to add a series output resistor (typically between 1 to 10 ). depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. power dissipation with the high-output drive capability of the el5220t amplifiers, it is possible to exceed the +150c absolute maximum junction temperature under certain load current conditions. it is important to calculate the maximum power dissipation of the el5220t in the application. proper load conditions will ensure that the el5220t junction temperature stays within a safe operating region. the maximum power dissipation allowed in a package is determined according to equation 1: where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation allowed the total power dissipation produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the ic due to the loads, or: when sourcing, and: when sinking, where: ? i = 1 to 2 (1, 2 corresponds to channel a, b respectively) ?v s = total supply voltage ( v s + - v s - ) ?v s + = positive supply voltage ?v s - = negative supply voltage ?i smax = maximum supply current per amplifier (i smax = el5220t quiescent current 2) ?v out = output voltage ?i load = load current device overheating can be avoided by calculating the minimum resistive load condition, r load , resulting in the highest power dissipation. to find r load set the two p dmax equations equal to each other and solve for v out /i load . reference the package power dissipation curves, figures 32 and 33, for further information. p dmax t jmax t amax ? ja -------------------------------------------- - = (eq. 1) p dmax iv [ s i smax v ( s +v out i ) i load i ? + ] = (eq. 2) p dmax iv [ s i smax v ( out iv s - ) i load i ? + ] = (eq. 3) 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 ambient temperature (c) power dissipation (w) figure 32. package power dissipation vs ambient temperature jedec jesd51-3 low effective thermal conductivity test board 85 781mw 595mw msop8 ja = +210c/w dfn8 ja = +160c/w 0.0 0.4 0.8 1.2 1.6 2.0 2.4 0 25 50 75 100 125 150 ambient temperature (c) power dissipation (w) figure 33. package power dissipation vs ambient temperature jedec jesd51-7 high effective thermal conductivity test board msop8 dfn8 2.16w 740mw 85 ja = +170c/w ja = +58c/w
el5220t 13 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www .intersil.com/design/qualit y intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www .intersil.com fn6892.0 may 4, 2010 for additional products, see www .intersil.com/product_tree power supply bypassing and printed circuit board layout the el5220t can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. for normal single supply operation (the v s - pin is connected to ground) a 4.7 f capacitor should be placed from v s + to ground, then a parallel 0.1 f capacitor should be connected as close to the amplifier as possible. one 4.7 f capacitor may be used for multiple devices. for dual supply operation the same capacitor combination should be placed at each supply pin to ground. it is highly recommended that el5220t exposed thermal pad packages should always have the pad connected to the lowest potential, v s -, to optimize thermal and operating performance. pcb vias should be placed below the device?s exposed thermal pad to transfer heat to the v s - plane and away from the device. products intersil corporation is a leader in the design and manufacture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www .intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation and related parts, please see the respective device information page on intersil.com: el5220t to report errors or suggestions for this datasheet, please go to www .intersil.com/ask ourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/4/10 fn6892.0 initial release
el5220t 14 fn6892.0 may 4, 2010 package outline drawing m8.118a 8 lead mini small outline plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions ?d? and ?e1? are measured at datum plane ?h?. this replaces existing drawing # mdp0043 msop 8l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to jedec mo-187-aa 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view side view 2 included. included. gauge plane 33 0.25 c a b b 0.10 c 0.08 c a b a 0.25 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 4.40 3.00 5.80 0.65 3.00.1 4.90.15 1.40 0.40 0.65 bsc pin# 1 id detail "x" 0.33 +0.07/ -0.08 0.10 0.05 3.00.1 1 2 8 0.860.09 seating plane and amse y14.5m-1994.
el5220t 15 fn6892.0 may 4, 2010 package outline drawing l8.2x3 8 lead dual flat no-lead plastic package rev 1, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.25mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view compies to jedec mo-229 vced-2. 7. (4x) 0.15 index area pin 1 pin #1 c seating plane base plane 0.08 see detail "x" c c 4 6 a b 0.90 0.10 0.05 max 0.05 max 0.20 ref 2.00 3.00 2x 1.50 8x 0.40 0.10 8x 0.25 +0.07/-0.05 index area 6x 0.50 (1.65) (1.50) (8x 0.60) (8x 0.25) (1.80) (2.80) (6x 0.50) 1 8 0.10 a mc b 0.10 c 1.80 +0.10/-0.15 1.65 +0.10/-0.15

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